Talantix.io
Astera Labs•06.03.26
AI SCORE 8.5

Expert IC Package Design Lead - Remote Opportunity

$150K–$200K/year
RemoteAI Infrastructure
IC Package Design•Cadence APD•Signal Integrity•Power Integrity•Thermal Analysis•Manufacturing Processes

About the Role

Astera Labs is seeking an Expert IC Package Design Lead to join our innovative team remotely. This role offers a unique opportunity to lead the development of advanced semiconductor packaging solutions that are critical for the future of AI at scale.

What You'll Do

  • Own the end-to-end IC package design process, from initial architecture to high-volume manufacturing.
  • Define package architecture and technology selection, including organic substrates and advanced laminate.
  • Lead signal integrity, power integrity, and thermal considerations for high-speed, high-power devices.
  • Drive package layout, substrate routing, and materials selection to meet stringent performance targets.
  • Collaborate with silicon design and manufacturing partners to optimize product performance.
  • Conduct risk assessments and lead failure analysis during production ramp-up.
  • Support new product introduction (NPI) and qualification activities, including vendor audits.

Requirements

  • 10+ years of hands-on IC package design experience for high-performance semiconductor products.
  • Expert proficiency in IC package design tools such as Cadence APD or equivalent.
  • Strong understanding of signal, power, and thermal integrity at the package level.
  • Proven experience in manufacturing and release processes, including DRC/LVS/DFM.
  • Familiarity with AI, networking, PCIe, and high-speed data center interfaces is preferred.

Nice to Have

  • Experience with chiplet-based architectures and heterogeneous integration.
  • Prior technical leadership on high-volume products.

What We Offer

  • Competitive salary and benefits package.
  • Remote work flexibility.
  • Opportunities for professional growth and development.
  • A diverse and inclusive work environment.
  • Engagement in cutting-edge AI infrastructure projects.
Why This Job8.5 of 10

Join Astera Labs as an Expert IC Package Design Lead and play a pivotal role in developing cutting-edge semiconductor solutions for AI. Enjoy remote work and a competitive salary.

Salary Range
Required
0/1
Optional
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Bonus
0/1

Who Will Succeed Here

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Proficiency in Cadence APD for IC package layout and design, with a strong understanding of signal integrity and power integrity principles to ensure optimal performance of semiconductor packages.

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A proactive and self-motivated work style suited for remote environments, with the ability to manage multiple projects effectively and collaborate across different teams and time zones.

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Extensive experience (8+ years) in semiconductor packaging processes, with a mindset geared towards innovation and continuous improvement in manufacturing techniques and thermal analysis.

Learning Resources

→Cadence APD User Guideguide
→Introduction to IC Package Designcourse
→Signal Integrity Basicsarticle

Career Path

Expert IC Package Design Lead(Now)→IC Package Design Manager(1-2 years)→Director of IC Packaging(3-5 years)

Market Overview

Market Size 2024
$5.2B
Annual Growth
8.5%
AI Adoption in IC Design
45%
Investment in Semiconductor Packaging
+25%
Labour Demand for IC Package Design
+15%
Avg Salary for IC Package Design Lead
$140K

Skills & Requirements

Required
IC Package DesignCadence APDSignal Integrity
Growing in Demand
3D IC DesignMachine Learning for Signal IntegrityAdvanced Thermal Management Techniques
Declining
Traditional PCB DesignManual Thermal Analysis

Domain Trends

Rise of 3D Packaging Technologies
3D packaging is expected to grow by 30% over the next 3 years, driven by the need for higher performance and miniaturization in electronic devices.
Increased Focus on Sustainability
Sustainable manufacturing processes in IC packaging are gaining traction, with 60% of companies investing in eco-friendly materials and processes.
Integration of AI in Design Processes
AI tools are being adopted by 45% of IC design firms to enhance signal integrity and thermal analysis, improving design accuracy and reducing time-to-market.

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